FIG. 15 illustrates a general construction of a prior typical circuit testing apparatus (circuit tester) of this kind. The circuit testing apparatus, denoted generally by reference numeral 10, comprises a pattern generator 11, a waveform generator 12 and a logical comparator 13. The waveform generator 12 generates a test pattern signal having a waveform necessary for testing a circuit under test DUT (or circuit to be tested), based on test pattern data included in pattern data which is outputted from the pattern generator 11. The test pattern signal generated by the waveform generator 12 is applied to a group of input terminals of the circuit under test DUT and the response outputs thereof are fed into the logical comparator 13. The logical comparator 13, which is supplied with expected value pattern data included in the pattern data from the pattern generator 11, performs a logical comparison between the expected value pattern data and the response outputs from the circuit under test DUT to sequentially detect whether there is an anti-coincidence between them, and when an anti-coincidence is detected by the logical comparator 13, a failure location of the circuit under test is specified or the like whereby the tested circuit is determined to be a "pass" (conforming circuit) or "failure" (non-conforming circuit).
Various kinds of pattern data including test pattern data, expected value pattern data and the like, which are outputted from the pattern generator 11 are prepared according to the function and scale of a circuit under test DUT, and/or the purpose of the test. Therefore, in case of testing a new kind of circuit device (IC or circuit device mounted on a board), pattern data (such as test pattern data, expected value pattern data, and the like) suitable for such new circuit device must be prepared. It is a general practice in the art to generate the pattern data by using a software, and as matters now stand, the development of the program therefor requires many hands and much time.
With an increase in the integration density of ICs, there is a tendency that an IC has functional blocks such as a memory, central processing means, a logic circuit, and the like integrated in the IC together with other integrated circuits. There are also cases where functional blocks such as a memory, central processing means, a logic circuit, and the like are mounted on a printed circuit board to form a circuit device. Since these functional blocks are interconnected in the IC or circuit board to operate, there is a disadvantage that the functional blocks cannot be tested individually or separately from the outside.
To enable independent testing of each functional block, there has been proposed such a scheme (or solution) that in addition to circuit wiring for actual operations of the functional blocks A, B, C and D, additional circuits RA, RB, RC and RD as well as additional circuits MA, MB, MC and MD are provided in correspondence with the functional blocks A, B, C and D, respectively, as shown in FIG. 16 and then test pattern data can be applied to each of the functional blocks through the additional circuits RA to RD and MA to MD and the corresponding response outputs can be taken out from the respective functional blocks, separately.
Now, this scheme will be described. The additional circuits MA to MD are storage parts that constitute a mode switching register. The outputs of the storage parts MA to MD forming the register are connected to respective mode switching terminals MOD of the corresponding functional blocks A to D as shown. In such construction, when it is desired to test only the functional block A, a serial data of "1, 0, 0, 0", for instance, is inputted to the register from an input terminal MT thereby storing a logic "1" in the additional circuit MA and a logic "0" in the remaining three additional circuits MB to MD. As a result, the storage output of the first-stage additional circuit MA, that is, the logic "1" is supplied to the mode switching terminal MOD of the corresponding functional block A, whereas the storage outputs of the second- to last-stage additional circuits MB to MD all of which are the logic "0" are supplied to the mode switching terminals MOD of the corresponding functional blocks B to D, respectively. Assuming, for example, that the logic "1" is an operation mode setting instruction for each functional block and the logic "0" an unoperation mode setting instruction, only the functional block A supplied with the logic "1" can be set in the operation mode and the remaining functional blocks B to D supplied with the logic "0" in the unoperation mode.
Next, resetting the additional circuits MA to MD and inputting a serial data of "0, 1, 0, 0" via the input terminal MT, only the functional block B is placed in the operation and the remaining functional blocks A, C and D in the unoperation mode. Thus, the functional blocks A to D can each be set in the operation mode independently of the others.
On the other hand, the additional circuits RA to RD constitute shift registers that have bits equal to the sums of the numbers of input and output terminals of the corresponding functional blocks A to D, respectively, and these shift registers are connected in cascade. With such construction, in the case of testing the functional block A, serialized test pattern signals to be fed to the functional block A are inputted through an input terminal PT and at a point in time when the test pattern signals have been shifted to the position where the test pattern signals can be given to all input terminals of the functional block A, the test pattern signals are inputted in parallel into the functional block A through its input terminals. The response outputs from the functional block A are read out in parallel to bit positions at the latter stage of the additional circuit (shift register) RA, and then the read-out response output signals are outputted in series and taken out from an output terminal QT via the remaining cascade-connected additional circuits RB to RD. Thus, the response outputs from the functional block A can be taken out. By converting the response outputs from the serial form into a parallel form, they can be compared with expected value pattern data in the logical comparator 13 provided in the circuit testing apparatus 10 to determine whether the functional block thus tested is a conforming ("pass") one or non-conforming ("failure") one.
As described above, a desired one of the functional blocks A to D can be tested independently by setting that one of the functional blocks A to D to the operation mode through the associated one of the additional circuits MA to MD, and thereafter supplying a serialized test pattern signals to the functional block set to the operation mode through the associated one off the additional circuits RA to RD, and taking out its response outputs in serial form via the output terminal QT, and converting the serial signal into a parallel signal.
FIG. 17 shows another example of the additional circuit. The illustrated example is used with a high-speed operating type functional block. The high-speed operating type functional block denoted by HSP may be a high-speed memory, for instance. To write data into and read it out of the high-speed memory, retiming circuits TMI.sub.1 and TMI.sub.2 are connected to the input and output sides of the memory, and the write and read of the memory are effected under the control of the retiming circuits TMI.sub.1 and TMI.sub.2, that is, by using an accurate timing produced by the retiming circuits TMI.sub.1 and TMI.sub.2.
In order to test the high-speed operating functional block HSP added with such additional circuits as the retiming circuits TMI.sub.1 and TMI.sub.2, it is necessary to give to the expected value pattern data a delay time produced by the additional circuits thereby matching the timing of the response output signal from the functional block with the timing of the expected value pattern data to provide them to the logical comparator 13.
As described above, in case the functional blocks to be tested are added with additional circuits, it is necessary in the circuit testing apparatus 10 that the pattern data to be generated from the pattern generator 11 are modified or altered corresponding to the differences between the various additional circuits. In particular, where test pattern data for application to each of the functional blocks A to D has already been developed, a program for generating the test pattern data needs to be developed again for each of the various additional circuits differing from one another, resulting in a serious economic loss.